The invention relates to a method for the manufacture of gate electrodes formed of double layers of metal silicides having a high melting point, and doped polycrystalline silicides (polycide), in particular for integrated complementary MOS-field effect transistor circuits (CMOS) wherein the manufacture of the source/drain zones is provided through ion implantation after the production of the gate electrode pursuant to use of the gate electrode as an implantation mask.
In order to increase switching and access times in integrated MOS-circuits, in modern processing n.sup.+ -polysilicon is replaced by a double layer formed by coating strongly phosphorous-doped polycrystalline silicon with a metal silicide having a high melting point; for example, tantalum disilicide, tungsten disilicide, or molybdenum silicide. Such double layers are designated as polycides. Their properties are discussed in an article by S. P. Murarka from J. Vac. Sci. Technol., 17 (4) July/August, 1980 on pages 775 to 792, incorporated herein by reference.
The high phosphorous concentration in polysilicon has a relatively thick natural oxide on the polysilicon which can lead to unreproducible polysilicon/silicide boundary surfaces or interferences. This obstructs the interface-reaction possibly necessary for the adjustment of the precise stoichiometry of the metal disilicides, influences the etching behavior and the oxidation of the polycides, as well as the loss of phosphor during subsequent temperature treatments. Fluctuating or even locally varying phosphor concentration in the polycide layer induces unreproducible etching and, primarily in the case of thermal re-oxidation, can lead to polycide damage. Moreover, a relatively thick polysilicon layer is required which brings about unnecessarily high steps in the polysilicon plane. As explained in an article by C. Koburger et al from the J. Electrochem. Soc., Vol. 129, No. 6 (1982), on pages 1307 to 1312, incorporated herein by reference, in the case of thinner layers, oxide breakthroughs occur in an increased fashion. Moreover, without a considerable increased expense, two conductivity types cannot be produced in the polysilicon plane which, in the case of CMOS-circuits, leads to relatively poor p-channel-properties (unfavorable work function). The use of n.sup.+ - and p.sup.+ -polysilicon without metal silicide on a chip makes available for n- and p-channel-MOS-field effect transistors, gates with a more favorable work function. However, it requires metal bridges between n.sup.+ - and p.sup.+ -polysilicon as well as additional masking steps.
The minimum demands of the polysilicon thickness could be made less stringent in the case of manufacture of polycides by use of molybdenum silicide (MOSi.sub.2) since first undoped polycrystalline silicon is employed which is doped only subsequent to the molybdenum disilicide deposition by ion implantation of phosphor. The thickness of the oxide (stratum oxide) resulting through thermal oxidation between polysilicon and silicide is reduced. Harmful local interface reactions are replaced by homogeneous reactions and no gate oxide damages occur any longer. Further details can be learned from a report by M. Fukumoto et al from Paper 7-7 in the Digest of Technical Papers of the 1983 Symposium on VLSI-technology, Hawaii, on pages 98/99, incorporated herein by reference.
A method of the initially cited type has been proposed in German patent application No. P 33 30 851.9,corresponding to U.S. Ser. No. 617,590, incorporated herein by reference. In the case of this method, the p-channel properties, given a specified low starting or threshold voltage can, indeed, be improved through use of a silicide gate (more favorable work function), whereby, however, the known favorable MOS properties of the polysilicon/SiO.sub.2 interface must be dispensed with.